Owen Yamauchi
c8cc07a61c
These rely on the hilarious BSR and BSF instructions on x64. ARMv8 has an instruction that does something similar: count leading zeros. Unfortunately, their semantics differ in a few important ways: - BSR and BSF, when given a zero input, set the zero flag and have undefined output. CLZ outputs 64. - BSR and BSF return the index (starting from 0 at the LSB) of the most- or least-significant 1 bit. CLZ does what it says: count leading zeros. Bottom line, there has to be some bit trickery somewhere to fit the two instructions into the same interface. I kept the x64 implementations the same and put all the nastiness in the ARM implementations to make them match, since obviously the perf of the ARM implementations doesn't matter yet.
81 linhas
2.6 KiB
C++
81 linhas
2.6 KiB
C++
/*
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+----------------------------------------------------------------------+
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| HipHop for PHP |
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+----------------------------------------------------------------------+
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| Copyright (c) 2010- Facebook, Inc. (http://www.facebook.com) |
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+----------------------------------------------------------------------+
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| This source file is subject to version 3.01 of the PHP license, |
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| that is bundled with this package in the file LICENSE, and is |
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| available through the world-wide-web at the following url: |
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| http://www.php.net/license/3_01.txt |
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| If you did not receive a copy of the PHP license and are unable to |
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| obtain it through the world-wide-web, please send a note to |
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| license@php.net so we can mail you a copy immediately. |
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+----------------------------------------------------------------------+
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*/
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#ifndef incl_BITOPS_H_
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#define incl_BITOPS_H_
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namespace HPHP {
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// GLIBC doesn't provide an fls primitive. Since we're rolling our own
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// anyway, fix ffs's wacky offset-by-one historical implementation. These
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// guys return success/failure (failure for input of all zeros) and the
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// unoffset bit position in their reference param.
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template<typename I64>
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inline bool ffs64(I64 input, I64 &out) {
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bool retval;
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#if defined(__x86_64__)
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asm volatile (
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"bsfq %2, %1\n\t" // bit scan forward
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"setnz %0\n\t": // zero retval if input == 0
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"=r"(retval), "=r"(out):
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"r"(input):
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"cc"
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);
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#elif defined(__AARCH64EL__)
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asm volatile (
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"rbit %2, %2\n\t" // reverse bits
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"clz %1, %2\n\t" // count leading zeros
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"cmp %1, #64\n\t"
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"cset %0, NE": // return (result != 64)
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"=r"(retval), "=r"(out), "+r"(input):
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:
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"cc"
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);
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#endif
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return retval;
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}
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template<typename I64>
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inline bool fls64(I64 input, I64 &out) {
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bool retval;
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#if defined(__x86_64__)
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asm volatile (
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"bsrq %2, %1\n\t" // bit scan reverse
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"setnz %0\n\t": // zero retval if input == 0
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"=r"(retval), "=r"(out):
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"r"(input):
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"cc"
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);
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#elif defined(__AARCH64EL__)
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asm volatile (
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"clz %1, %2\n\t" // count leading zeros
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"neg %1, %1\n\t"
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"adds %1, %1, #63\n\t" // result = 63 - (# of leading zeros)
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// "s" suffix sets condition flags
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"cset %0, PL": // return (result >= 0)
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// because result < 0 iff input == 0
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"=r"(retval), "=r"(out):
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"r"(input):
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"cc"
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);
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#endif
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return retval;
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}
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} // HPHP
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#endif
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