bsimmers
f928f1b320
This was going to be easy, but then it wasn't. The existing interpOne relied heavily on the outputs of NormalizedInstruction, and those are only populated by code that we want to kill soon. It also didn't properly deal with bytecodes that wrote to more than one local, or more than one stack cell. So the bulk of this diff is rewriting interpOne to not rely on the NI outputs, then it was simple to hook it into the region translator. I also cleaned things up so we don't attempt to translate instructions that have no hope of succeeding; we just interp them on the first try now.
574 linhas
19 KiB
C++
574 linhas
19 KiB
C++
/*
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+----------------------------------------------------------------------+
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| HipHop for PHP |
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+----------------------------------------------------------------------+
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| Copyright (c) 2010-2013 Facebook, Inc. (http://www.facebook.com) |
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+----------------------------------------------------------------------+
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| This source file is subject to version 3.01 of the PHP license, |
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| that is bundled with this package in the file LICENSE, and is |
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| available through the world-wide-web at the following url: |
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| http://www.php.net/license/3_01.txt |
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| If you did not receive a copy of the PHP license and are unable to |
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| obtain it through the world-wide-web, please send a note to |
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| license@php.net so we can mail you a copy immediately. |
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+----------------------------------------------------------------------+
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*/
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#ifndef incl_HPHP_VM_CG_H_
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#define incl_HPHP_VM_CG_H_
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#include <vector>
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#include "hphp/runtime/vm/jit/ir.h"
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#include "hphp/runtime/vm/jit/irfactory.h"
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#include "hphp/runtime/vm/jit/linearscan.h"
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#include "hphp/runtime/vm/jit/targetcache.h"
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#include "hphp/runtime/vm/jit/translator-x64.h"
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#include "hphp/runtime/vm/jit/state_vector.h"
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namespace HPHP {
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namespace JIT {
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struct ArgGroup;
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// DestType describes the return type of native helper calls, particularly
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// register assignments
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enum class DestType : unsigned {
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None, // return void (no valid registers)
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SSA, // return a single-register value
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TV // return a TypedValue packed in two registers
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};
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enum class SyncOptions {
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kNoSyncPoint,
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kSyncPoint,
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kSyncPointAdjustOne,
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};
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// Information about where code was generated, for pretty-printing.
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struct AsmInfo {
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explicit AsmInfo(const IRFactory* factory)
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: instRanges(factory, TcaRange(nullptr, nullptr))
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, asmRanges(factory, TcaRange(nullptr, nullptr))
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, astubRanges(factory, TcaRange(nullptr, nullptr))
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{}
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// Asm address info for each instruction and block
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StateVector<IRInstruction,TcaRange> instRanges;
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StateVector<Block,TcaRange> asmRanges;
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StateVector<Block,TcaRange> astubRanges;
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};
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typedef StateVector<IRInstruction, RegSet> LiveRegs;
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// Stuff we need to preserve between blocks while generating code,
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// and address information produced during codegen.
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struct CodegenState {
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CodegenState(const IRFactory* factory, const RegAllocInfo& regs,
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const LiveRegs& liveRegs, const LifetimeInfo* lifetime,
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AsmInfo* asmInfo)
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: patches(factory, nullptr)
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, addresses(factory, nullptr)
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, lastMarker(nullptr)
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, regs(regs)
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, liveRegs(liveRegs)
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, lifetime(lifetime)
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, asmInfo(asmInfo)
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, catches(factory, CatchInfo())
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, catchTrace(nullptr)
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{}
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// Each block has a list of addresses to patch, and an address if
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// it's already been emitted.
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StateVector<Block,void*> patches;
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StateVector<Block,TCA> addresses;
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// Keep track of the most recent Marker instruction we've seen in the
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// current trace (even across blocks).
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const MarkerData* lastMarker;
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// True if this block's terminal Jmp_ has a desination equal to the
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// next block in the same assmbler.
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bool noTerminalJmp_;
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// output from register allocator
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const RegAllocInfo& regs;
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// for each instruction, holds the RegSet of registers that must be
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// preserved across that instruction. This is for push/pop of caller-saved
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// registers.
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const LiveRegs& liveRegs;
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// Optional information used when pretty-printing code after codegen.
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// when not available, these are nullptrs.
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const LifetimeInfo* lifetime;
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// Output: start/end ranges of machine code addresses of each instruction.
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AsmInfo* asmInfo;
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// Used to pass information about the state of the world at native
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// calls between cgCallHelper and cgBeginCatch.
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StateVector<Block, CatchInfo> catches;
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// If non-null, represents the catch trace for the current
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// instruction, to be registered with the unwinder.
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IRTrace* catchTrace;
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};
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constexpr Reg64 rCgGP (reg::r11);
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constexpr RegXMM rCgXMM0(reg::xmm0);
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constexpr RegXMM rCgXMM1(reg::xmm1);
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struct CodeGenerator {
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typedef Transl::X64Assembler Asm;
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CodeGenerator(IRTrace* trace, Asm& as, Asm& astubs,
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Transl::TranslatorX64* tx64, CodegenState& state)
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: m_as(as)
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, m_astubs(astubs)
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, m_tx64(tx64)
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, m_state(state)
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, m_regs(state.regs)
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, m_rScratch(InvalidReg)
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, m_curInst(nullptr)
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, m_curTrace(trace)
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, m_curBcOff(-1) {
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}
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void cgBlock(Block* block, vector<TransBCMapping>* bcMap);
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private:
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Address cgInst(IRInstruction* inst);
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// Autogenerate function declarations for each IR instruction in ir.h
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#define O(name, dsts, srcs, flags) void cg##name(IRInstruction* inst);
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IR_OPCODES
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#undef O
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// helper functions for code generation
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void cgCallNative(IRInstruction* inst) {
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cgCallNative(m_as, inst);
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}
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void cgCallNative(Asm& a, IRInstruction* inst);
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void doStackArgs(Asm&, ArgGroup&);
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void cgCallHelper(Asm&,
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TCA addr,
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SSATmp* dst,
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SyncOptions sync,
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ArgGroup& args,
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DestType destType = DestType::SSA);
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void cgCallHelper(Asm& a,
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TCA addr,
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PhysReg dstReg,
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SyncOptions sync,
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ArgGroup& args,
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DestType destType = DestType::SSA);
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void cgCallHelper(Asm& a,
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const Transl::CppCall& call,
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PhysReg dstReg,
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SyncOptions sync,
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ArgGroup& args,
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DestType destType = DestType::SSA);
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void cgCallHelper(Asm& a,
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const Transl::CppCall& call,
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PhysReg dstReg0,
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PhysReg dstReg1,
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SyncOptions sync,
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ArgGroup& args,
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DestType destType = DestType::SSA);
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void cgCallHelper(Asm& a,
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const Transl::CppCall& call,
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PhysReg dstReg0,
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PhysReg dstReg1,
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SyncOptions sync,
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ArgGroup& args,
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RegSet toSave,
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DestType destType = DestType::SSA);
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void cgStore(PhysReg base,
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int64_t off,
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SSATmp* src,
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bool genStoreType = true);
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void cgStoreTypedValue(PhysReg base, int64_t off, SSATmp* src);
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void cgLoad(PhysReg base, int64_t off, IRInstruction* inst);
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template<class Loc1, class Loc2, class JmpFn>
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void emitTypeTest(Type type,
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Loc1 typeSrc,
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Loc2 dataSrc,
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JmpFn doJcc);
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template<class Loc>
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void emitTypeCheck(Type type, Loc typeSrc, Loc dataSrc, Block* taken);
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template<class Loc>
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void emitTypeGuard(Type type, Loc typeLoc, Loc dataLoc);
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void cgStMemWork(IRInstruction* inst, bool genStoreType);
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void cgStRefWork(IRInstruction* inst, bool genStoreType);
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void cgStPropWork(IRInstruction* inst, bool genStoreType);
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void cgIncRefWork(Type type, SSATmp* src);
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void cgDecRefWork(IRInstruction* inst, bool genZeroCheck);
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template<class OpInstr, class Oper>
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void cgUnaryIntOp(SSATmp* dst, SSATmp* src, OpInstr, Oper);
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enum Commutativity { Commutative, NonCommutative };
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template<class Oper, class RegType>
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void cgBinaryOp(IRInstruction*,
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void (Asm::*intImm)(Immed, RegType),
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void (Asm::*intRR)(RegType, RegType),
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void (Asm::*mov)(RegType, RegType),
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void (Asm::*fpRR)(RegXMM, RegXMM),
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Oper,
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RegType (*conv)(PhysReg),
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Commutativity);
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template<class Oper, class RegType>
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void cgBinaryIntOp(IRInstruction*,
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void (Asm::*intImm)(Immed, RegType),
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void (Asm::*intRR)(RegType, RegType),
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void (Asm::*mov)(RegType, RegType),
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Oper,
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RegType (*conv)(PhysReg),
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Commutativity);
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void cgNegateWork(SSATmp* dst, SSATmp* src);
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void cgNotWork(SSATmp* dst, SSATmp* src);
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void emitGetCtxFwdCallWithThis(PhysReg ctxReg,
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bool staticCallee);
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void emitGetCtxFwdCallWithThisDyn(PhysReg destCtxReg,
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PhysReg thisReg,
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Transl::TargetCache::CacheHandle& ch);
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void cgLoadTypedValue(PhysReg base, int64_t off, IRInstruction* inst);
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void cgJcc(IRInstruction* inst); // helper
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void cgReqBindJcc(IRInstruction* inst); // helper
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void cgOpCmpHelper(
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IRInstruction* inst,
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void (Asm::*setter)(Reg8),
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int64_t (*str_cmp_str)(StringData*, StringData*),
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int64_t (*str_cmp_int)(StringData*, int64_t),
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int64_t (*str_cmp_obj)(StringData*, ObjectData*),
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int64_t (*obj_cmp_obj)(ObjectData*, ObjectData*),
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int64_t (*obj_cmp_int)(ObjectData*, int64_t),
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int64_t (*arr_cmp_arr)(ArrayData*, ArrayData*));
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template<class Loc>
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void emitSideExitGuard(Type type, Loc typeLoc,
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Loc dataLoc, Offset taken);
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void emitReqBindJcc(ConditionCode cc, const ReqBindJccData*);
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void emitCompare(SSATmp*, SSATmp*);
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void emitTestZero(SSATmp*);
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bool emitIncDecHelper(SSATmp* dst, SSATmp* src1, SSATmp* src2,
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void(Asm::*emitFunc)(Reg64));
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bool emitInc(SSATmp* dst, SSATmp* src1, SSATmp* src2);
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bool emitDec(SSATmp* dst, SSATmp* src1, SSATmp* src2);
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private:
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PhysReg selectScratchReg(IRInstruction* inst);
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void emitLoadImm(CodeGenerator::Asm& as, int64_t val, PhysReg dstReg);
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PhysReg prepXMMReg(const SSATmp* tmp,
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X64Assembler& as,
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const RegAllocInfo& allocInfo,
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RegXMM rXMMScratch);
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void emitSetCc(IRInstruction*, ConditionCode);
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template<class JmpFn>
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void emitIsTypeTest(IRInstruction* inst, JmpFn doJcc);
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void doubleCmp(X64Assembler& a, RegXMM xmmReg0, RegXMM xmmReg1);
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void cgIsTypeCommon(IRInstruction* inst, bool negate);
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void cgJmpIsTypeCommon(IRInstruction* inst, bool negate);
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void cgIsTypeMemCommon(IRInstruction*, bool negate);
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void emitInstanceBitmaskCheck(IRInstruction*);
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void emitTraceRet(CodeGenerator::Asm& as);
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Address cgCheckStaticBit(Type type,
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PhysReg reg,
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bool regIsCount);
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Address cgCheckStaticBitAndDecRef(Type type,
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PhysReg dataReg,
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Block* exit);
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Address cgCheckRefCountedType(PhysReg typeReg);
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Address cgCheckRefCountedType(PhysReg baseReg,
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int64_t offset);
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void cgDecRefStaticType(Type type,
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PhysReg dataReg,
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Block* exit,
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bool genZeroCheck);
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void cgDecRefDynamicType(PhysReg typeReg,
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PhysReg dataReg,
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Block* exit,
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bool genZeroCheck);
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void cgDecRefDynamicTypeMem(PhysReg baseReg,
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int64_t offset,
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Block* exit);
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void cgDecRefMem(Type type,
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PhysReg baseReg,
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int64_t offset,
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Block* exit);
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void cgIterNextCommon(IRInstruction* inst);
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void cgIterInitCommon(IRInstruction* inst);
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void cgLdFuncCachedCommon(IRInstruction* inst);
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TargetCache::CacheHandle cgLdClsCachedCommon(IRInstruction* inst);
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void emitFwdJcc(ConditionCode cc, Block* target);
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void emitFwdJcc(Asm& a, ConditionCode cc, Block* target);
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void emitContVarEnvHelperCall(SSATmp* fp, TCA helper);
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const Func* curFunc() const;
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Class* curClass() const { return curFunc()->cls(); }
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void recordSyncPoint(Asm& as, SyncOptions sync = SyncOptions::kSyncPoint);
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Address getDtorGeneric();
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Address getDtorTyped();
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int iterOffset(SSATmp* tmp);
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int iterOffset(uint32_t id);
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void emitReqBindAddr(const Func* func, TCA& dest, Offset offset);
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void emitAdjustSp(PhysReg spReg, PhysReg dstReg, int64_t adjustment);
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void emitConvBoolOrIntToDbl(IRInstruction* inst);
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/*
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* Generate an if-block that branches around some unlikely code, handling
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* the cases when a == astubs and a != astubs. cc is the branch condition
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* to run the unlikely block.
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*
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* Passes the proper assembler to use to the unlikely function.
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*/
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template <class Block>
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void unlikelyIfBlock(ConditionCode cc, Block unlikely) {
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if (&m_as == &m_astubs) {
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Label done;
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m_as.jcc(ccNegate(cc), done);
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unlikely(m_as);
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asm_label(m_as, done);
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} else {
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Label unlikelyLabel, done;
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m_as.jcc(cc, unlikelyLabel);
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asm_label(m_astubs, unlikelyLabel);
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unlikely(m_astubs);
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m_astubs.jmp(done);
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asm_label(m_as, done);
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}
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}
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// Generate an if-then-else block into m_as.
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template <class Then, class Else>
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void ifThenElse(ConditionCode cc, Then thenBlock, Else elseBlock) {
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Label elseLabel, done;
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m_as.jcc8(ccNegate(cc), elseLabel);
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thenBlock();
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m_as.jmp8(done);
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asm_label(m_as, elseLabel);
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elseBlock();
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asm_label(m_as, done);
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}
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// This is for printing partially-generated traces when debugging
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void print() const;
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private:
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Asm& m_as; // current "main" assembler
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Asm& m_astubs; // assembler for stubs and other cold code.
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TranslatorX64* m_tx64;
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CodegenState& m_state;
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const RegAllocInfo& m_regs;
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Reg64 m_rScratch; // currently selected GP scratch reg
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IRInstruction* m_curInst; // current instruction being generated
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IRTrace* m_curTrace;
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uint32_t m_curBcOff; // offset of bytecode instr that produced
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// m_curInst
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};
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class ArgDesc {
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public:
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enum class Kind {
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Reg, // Normal register
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TypeReg, // TypedValue's m_type field. Might need arch-specific
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// mangling before call depending on TypedValue's layout.
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Imm, // Immediate
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Addr, // Address
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None, // Nothing: register will contain garbage
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};
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PhysReg dstReg() const { return m_dstReg; }
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PhysReg srcReg() const { return m_srcReg; }
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Kind kind() const { return m_kind; }
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void setDstReg(PhysReg reg) { m_dstReg = reg; }
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Immed imm() const { return m_imm; }
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bool isZeroExtend() const {return m_zeroExtend;}
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bool done() const { return m_done; }
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void markDone() { m_done = true; }
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private: // These should be created using ArgGroup.
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friend struct ArgGroup;
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explicit ArgDesc(Kind kind, PhysReg srcReg, Immed immVal)
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: m_kind(kind)
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, m_srcReg(srcReg)
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, m_dstReg(reg::noreg)
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, m_imm(immVal)
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, m_zeroExtend(false)
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, m_done(false)
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{}
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explicit ArgDesc(SSATmp* tmp, const RegisterInfo& info, bool val = true);
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private:
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Kind m_kind;
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PhysReg m_srcReg;
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PhysReg m_dstReg;
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Immed m_imm;
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bool m_zeroExtend;
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bool m_done;
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};
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/*
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* Bag of ArgDesc for use with cgCallHelper.
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*
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* You can create this using function chaining. Example:
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*
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* ArgGroup args;
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* args.imm(0)
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* .reg(rax)
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* .immPtr(StringData::GetStaticString("Yo"))
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* ;
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* assert(args.size() == 3);
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*/
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struct ArgGroup {
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typedef std::vector<ArgDesc> ArgVec;
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explicit ArgGroup(const RegAllocInfo& regs)
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: m_regs(regs), m_override(nullptr)
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{}
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size_t numRegArgs() const { return m_regArgs.size(); }
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size_t numStackArgs() const { return m_stkArgs.size(); }
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ArgDesc& reg(size_t i) {
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assert(i < m_regArgs.size());
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return m_regArgs[i];
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}
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ArgDesc& operator[](size_t i) {
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return reg(i);
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}
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ArgDesc& stk(size_t i) {
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assert(i < m_stkArgs.size());
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return m_stkArgs[i];
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}
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ArgGroup& imm(uintptr_t imm) {
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push_arg(ArgDesc(ArgDesc::Kind::Imm, InvalidReg, imm));
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return *this;
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}
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template<class T> ArgGroup& immPtr(const T* ptr) {
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return imm(uintptr_t(ptr));
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}
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ArgGroup& immPtr(std::nullptr_t) { return imm(0); }
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ArgGroup& reg(PhysReg reg) {
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push_arg(ArgDesc(ArgDesc::Kind::Reg, PhysReg(reg), -1));
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return *this;
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}
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ArgGroup& addr(PhysReg base, intptr_t off) {
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push_arg(ArgDesc(ArgDesc::Kind::Addr, base, off));
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return *this;
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}
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ArgGroup& ssa(SSATmp* tmp) {
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push_arg(ArgDesc(tmp, m_regs[tmp]));
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return *this;
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}
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|
|
ArgGroup& ssas(IRInstruction* inst, unsigned begin, unsigned count = 1) {
|
|
for (SSATmp* s : inst->srcs().subpiece(begin, count)) {
|
|
push_arg(ArgDesc(s, m_regs[s]));
|
|
}
|
|
return *this;
|
|
}
|
|
|
|
/*
|
|
* Pass tmp as a TypedValue passed by value.
|
|
*/
|
|
ArgGroup& typedValue(SSATmp* tmp) {
|
|
// If there's exactly one register argument slot left, the whole TypedValue
|
|
// goes on the stack instead of being split between a register and the
|
|
// stack.
|
|
if (m_regArgs.size() == kNumRegisterArgs - 1) {
|
|
m_override = &m_stkArgs;
|
|
}
|
|
packed_tv ? type(tmp).ssa(tmp) : ssa(tmp).type(tmp);
|
|
m_override = nullptr;
|
|
return *this;
|
|
}
|
|
|
|
ArgGroup& vectorKeyIS(SSATmp* key) {
|
|
return vectorKeyImpl(key, true);
|
|
}
|
|
|
|
ArgGroup& vectorKeyS(SSATmp* key) {
|
|
return vectorKeyImpl(key, false);
|
|
}
|
|
|
|
private:
|
|
void push_arg(const ArgDesc& arg) {
|
|
// If m_override is set, use it unconditionally. Otherwise, select
|
|
// m_regArgs or m_stkArgs depending on how many args we've already pushed.
|
|
ArgVec* args = m_override;
|
|
if (!args) {
|
|
args = m_regArgs.size() < kNumRegisterArgs ? &m_regArgs : &m_stkArgs;
|
|
}
|
|
args->push_back(arg);
|
|
}
|
|
|
|
/*
|
|
* For passing the m_type field of a TypedValue.
|
|
*/
|
|
ArgGroup& type(SSATmp* tmp) {
|
|
push_arg(ArgDesc(tmp, m_regs[tmp], false));
|
|
return *this;
|
|
}
|
|
|
|
ArgGroup& none() {
|
|
push_arg(ArgDesc(ArgDesc::Kind::None, InvalidReg, -1));
|
|
return *this;
|
|
}
|
|
|
|
ArgGroup& vectorKeyImpl(SSATmp* key, bool allowInt) {
|
|
if (key->isString() || (allowInt && key->isA(Type::Int))) {
|
|
return packed_tv ? none().ssa(key) : ssa(key).none();
|
|
}
|
|
return typedValue(key);
|
|
}
|
|
|
|
const RegAllocInfo& m_regs;
|
|
ArgVec* m_override; // used to force args to go into a specific ArgVec
|
|
ArgVec m_regArgs;
|
|
ArgVec m_stkArgs;
|
|
};
|
|
|
|
const Func* loadClassCtor(Class* cls);
|
|
|
|
Instance* createClHelper(Class*, int, ActRec*, TypedValue*);
|
|
|
|
void genCodeForTrace(IRTrace* trace,
|
|
CodeGenerator::Asm& a,
|
|
CodeGenerator::Asm& astubs,
|
|
IRFactory* irFactory,
|
|
vector<TransBCMapping>* bcMap,
|
|
TranslatorX64* tx64,
|
|
const RegAllocInfo& regs,
|
|
const LifetimeInfo* lifetime = nullptr,
|
|
AsmInfo* asmInfo = nullptr);
|
|
|
|
TypedValue arrayIdxI(ArrayData*, int64_t, TypedValue);
|
|
TypedValue arrayIdxS(ArrayData*, StringData*, TypedValue);
|
|
TypedValue arrayIdxSi(ArrayData*, StringData*, TypedValue);
|
|
|
|
}}
|
|
|
|
#endif
|