Abdulla Kamar
627e15ffbf
Add code to manage EL2 CPU state. Currently this does the very minimum and sets the EL2 stack for each CPU. Next, I'll start setting up more of the EL2 state and also guest physical address space. Change-Id: I18b7f9d00b236e52cdc317dffe3b42fcffbcb8fe
143 linhas
3.0 KiB
ArmAsm
143 linhas
3.0 KiB
ArmAsm
// Copyright 2016 The Fuchsia Authors
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// Copyright (c) 2014 Travis Geiselbrecht
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//
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// Use of this source code is governed by a MIT-style
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// license that can be found in the LICENSE file or at
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// https://opensource.org/licenses/MIT
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#include <asm.h>
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#include <arch/asm_macros.h>
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#define HCR_EL2_RW (1 << 31)
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#define SCR_EL3_HCE (1 << 1)
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#define SCR_EL3_RW (1 << 10)
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/* void arm64_context_switch(vaddr_t *old_sp, vaddr_t new_sp); */
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FUNCTION(arm64_context_switch)
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/* save old frame */
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/* This layout should match struct context_switch_frame */
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push_regs x29, x30
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push_regs x27, x28
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push_regs x25, x26
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push_regs x23, x24
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push_regs x21, x22
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push_regs x19, x20
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mrs x19, tpidr_el0
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mrs x20, tpidrro_el0
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push_regs x19, x20
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/* save old sp */
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mov x15, sp
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str x15, [x0]
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/* load new sp */
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mov sp, x1
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/* restore new frame */
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pop_regs x19, x20
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msr tpidr_el0, x19
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msr tpidrro_el0, x20
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pop_regs x19, x20
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pop_regs x21, x22
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pop_regs x23, x24
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pop_regs x25, x26
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pop_regs x27, x28
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pop_regs x29, x30
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ret
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END_FUNCTION(arm64_context_switch)
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FUNCTION(arm64_elX_to_el1)
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mrs x9, CurrentEL
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cmp x9, #(0b01 << 2)
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bne .notEL1
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/* Already in EL1 */
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ret
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.notEL1:
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cmp x9, #(0b10 << 2)
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beq .inEL2
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/* set EL2 to 64bit and enable HVC instruction */
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mrs x9, scr_el3
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orr x9, x9, #SCR_EL3_HCE
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orr x9, x9, #SCR_EL3_RW
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msr scr_el3, x9
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adr x9, .Ltarget
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msr elr_el3, x9
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mov x9, #((0b1111 << 6) | (0b0101)) /* EL1h runlevel */
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msr spsr_el3, x9
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b .confEL1
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.inEL2:
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/* Set the vector base for EL2 */
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adr_global x9, arm64_el2_exception_base
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msr vbar_el2, x9
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/* Ensure EL1 timers are properly configured, disable EL2 trapping of
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EL1 access to timer control registers. Also clear virtual offset.
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*/
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mrs x9, cnthctl_el2
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orr x9, x9, #3
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msr cnthctl_el2, x9
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msr cntvoff_el2, xzr
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/* clear out stage 2 translations */
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msr vttbr_el2, xzr
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adr x9, .Ltarget
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msr elr_el2, x9
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mov x9, #((0b1111 << 6) | (0b0101)) /* EL1h runlevel */
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msr spsr_el2, x9
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.confEL1:
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/* disable EL2 coprocessor traps */
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mov x9, #0x33ff
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msr cptr_el2, x9
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/* set EL1 to 64bit */
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mov x9, #HCR_EL2_RW
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msr hcr_el2, x9
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/* disable EL1 FPU traps */
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mov x9, #(0b11<<20)
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msr cpacr_el1, x9
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/* set up the EL1 bounce interrupt */
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mov x9, sp
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msr sp_el1, x9
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isb
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eret
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.Ltarget:
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ret
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END_FUNCTION(arm64_elX_to_el1)
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FUNCTION(arm64_get_secondary_sp)
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mrs x9, mpidr_el1
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and x9, x9, #0xffff /* only use id/cluster */
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mov x10, #SMP_MAX_CPUS
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adr_global x11, arm64_secondary_sp_list
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.Lsp_loop:
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ldr x12, [x11, #0]
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cmp x12, x9
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beq .Lsp_found
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add x11, x11, #32
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subs x10, x10, #1
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bne .Lsp_loop
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mov x0, xzr
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mov x1, xzr
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ret
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.Lsp_found:
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ldr x0, [x11, #8]
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add x1, x11, #32
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ret
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END_FUNCTION(arm64_get_secondary_sp)
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